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19-3259; Rev 0; 5/04
KIT ATION EVALU LE B AVAILA
40Msps, 12-Bit ADC
General Description Features
o Excellent Dynamic Performance 68.6dB SNR at fIN = 20MHz 90dBc SFDR at fIN = 20MHz o Low-Power Operation 159mW at 3.0V (Single-Ended Clock) 181mW at 3.3V (Single-Ended Clock) 198mW at 3.3V (Differential Clock) o Differential or Single-Ended Clock o Accepts 20% to 80% Clock Duty Cycle o Fully Differential or Single-Ended Analog Input o Adjustable Full-Scale Analog Input Range o Common-Mode Reference o Power-Down Mode o CMOS-Compatible Outputs in Two's Complement or Gray Code o Data-Valid Indicator Simplifies Digital Design o Out-of-Range and Data-Valid Indicators o Miniature, 40-Pin Thin QFN Package with Exposed Paddle o Pin-Compatible, IF Sampling ADC Available (MAX1211ETL) o Evaluation Kit Available (Order MAX1211EVKIT)
MAX1206
The MAX1206 is a 3.3V, 12-bit analog-to-digital converter (ADC) featuring a fully differential wideband track-andhold (T/H) input, driving the internal quantizer. The MAX1206 is optimized for low power, small size, and high dynamic performance. This ADC operates from a single 3.0V to 3.6V supply, consuming only 159mW, while delivering a typical signal-to-noise ratio (SNR) performance of 68.6dB at a 20MHz input frequency. The T/H-driven input stage accepts single-ended or differential inputs. In addition to low operating power, the MAX1206 features a 0.15mW power-down mode to conserve power during idle periods. A flexible reference structure allows the MAX1206 to use its internal precision bandgap reference or accept an externally applied reference. A common-mode reference is provided to simplify design and reduce external component count in differential analog input circuits. The MAX1206 supports both a single-ended and differential input clock drive. Wide variations in the clock duty cycle are compensated with the ADC's internal duty-cycle equalizer. The MAX1206 features parallel, CMOS-compatible outputs. The digital output format is pin selectable to be either two's complement or Gray code. A data-valid indicator eliminates external components that are normally required for reliable digital interfacing. A separate power input for the digital outputs accepts a voltage from 1.7V to 3.6V for flexible interfacing with various logic levels. The MAX1206 is available in a 6mm x 6mm x 0.8mm, 40pin thin QFN package with exposed paddle (EP), and is specified for the extended industrial (-40C to +85C) temperature range. Refer to the MAX1209 and MAX1211 (see Pin-Compatible Higher/Speed Versions table) for applications that require high dynamic performance for IF input frequencies.
Ordering Information
PART MAX1206ETL TEMP RANGE -40C to +85C PIN-PACKAGE 40 Thin QFN (6mm x 6mm)
Applications
Communication Receivers Cellular, LMDS, Point-to-Point Microwave, MMDS, HFC, WLAN Ultrasound and Medical Imaging Portable Instrumentation Low-Power Data Acquisition
PART MAX1206 MAX1207 MAX1208 MAX1211 MAX1209
Pin-Compatible Higher Speed Versions
SPEED GRADE (Msps) 40 65 80 65 80 TARGET APPLICATION Baseband Baseband Baseband IF IF
Pin Configuration appears at end of data sheet. ________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
40Msps, 12-Bit ADC MAX1206
ABSOLUTE MAXIMUM RATINGS
VDD to GND ...........................................................-0.3V to +3.6V OVDD to GND........-0.3V to the lower of (VDD + 0.3V) and +3.6V INP, INN to GND ...-0.3V to the lower of (VDD + 0.3V) and +3.6V REFIN, REFOUT, REFP, REFN, COM to GND.....-0.3V to the lower of (VDD + 0.3V) and +3.6V CLKP, CLKN, CLKTYP, G/T, DCE, PD to GND ........-0.3V to the lower of (VDD + 0.3V) and +3.6V D11-D0, I.C., DAV, DOR to GND ............-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70C) 40-Pin Thin QFN 6mm x 6mm x 0.8mm (derated 26.3mW/C above +70C)........................2105.3mW Operating Temperature Range ...........................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering 10s) ..................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CREFOUT = 0.1F, CL 5pF at digital outputs, VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 40MHz (50% duty cycle), CREFP = CREFN = 0.1F to GND, 1F in parallel with 10F between REFP and REFN, CCOM = 0.1F in parallel with 2.2F to GND, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error ANALOG INPUT (INP, INN) Differential Input Voltage Range Common-Mode Input Voltage Input Resistance Input Capacitance CONVERSION RATE Maximum Clock Frequency Minimum Clock Frequency Data Latency Figure 5 8.5 fCLK 40 5 MHz MHz Clock cycles RIN CIN Switched capacitor load VDIFF Differential or single-ended inputs 1.024 VDD / 2 24 4 V V k pF INL DNL fIN = 20MHz (Note 2) fIN = 20MHz, no missing codes over temperature (Note 2) VREFIN = 2.048V VREFIN = 2.048V 12 0.3 0.3 0.2 0.3 0.7 0.7 1.1 4.8 Bits LSB LSB %FS %FS SYMBOL CONDITIONS MIN TYP MAX UNITS
DYNAMIC CHARACTERISTICS (Differential inputs, 4096-point FFT) Signal-to-Noise Ratio Signal-to-Noise and Distortion Single-Tone Spurious-Free Dynamic Range Total Harmonic Distortion SNR SINAD SFDR THD fIN = 3MHz at -0.5dBFS fIN = 20MHz at -0.5dBFS (Note 2) fIN = 3MHz at -0.5dBFS fIN = 20MHz at -0.5dBFS (Note 2) fIN = 3MHz at -0.5dBFS fIN = 20MHz at -0.5dBFS (Note 2) fIN = 3MHz at -0.5dBFS fIN = 20MHz at -0.5dBFS (Note 2) 83.2 66.9 67.0 68.4 68.6 68.3 68.5 89.5 90 -88.4 -88.4 -81 dB dB dBc dBc
2
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40Msps, 12-Bit ADC
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CREFOUT = 0.1F, CL 5pF at digital outputs, VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 40MHz (50% duty cycle), CREFP = CREFN = 0.1F to GND, 1F in parallel with 10F between REFP and REFN, CCOM = 0.1F in parallel with 2.2F to GND, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Second Harmonic Third Harmonic Third-Order Intermodulation Two-Tone Spurious-Free Dynamic Range Aperture Delay Aperture Jitter Output Noise Overdrive Recovery Time SYMBOL HD2 HD3 IM3 SFDRTT tAD tAJ nOUT CONDITIONS fIN = 3MHz at -0.5dBFS fIN = 20MHz at -0.5dBFS (Note 3) fIN = 3MHz at -0.5dBFS fIN = 20MHz at -0.5dBFS (Note 3) fIN1 = 69MHz at -7dBFS, fIN2 = 71MHz at -7dBFS fIN1 = 69MHz at -7dBFS, fIN2 = 71MHz at -7dBFS Figure 14 Figure 14 INP = INN = COM 10% beyond full scale MIN TYP -92.5 -96.3 -93.8 -92.1 -89 88 0.9 <0.2 0.5 1 -83.3 -84.9 MAX UNITS dBc dBc dBc dBc ns psRMS LSBRMS Clock cycles 2.080 V V V mV/mA ppm/C mA
MAX1206
INTERNAL REFERENCE (REFIN = REFOUT; VREFP, VREFN, and VCOM are generated internally) REFOUT Output Voltage COM Output Voltage Differential Reference Output Voltage REFOUT Load Regulation REFOUT Temperature Coefficient REFOUT Short-Circuit Current TCREF Short to VDD Short to GND VREFIN VREFP VREFN VCOM VREF (VDD / 2) + (VREFIN / 4) (VDD / 2) - (VREFIN / 4) VDD / 2 VREF = VREFP - VREFN 1.60 0.970 VREFOUT VCOM VREF VDD / 2 VREF = VREFP - VREFN 1.988 2.048 1.65 1.024 35 +100 0.24 2.1 2.048 2.162 1.138 1.65 1.024 +12.5 IREFP IREFN ICOM Source Sink Source Sink Source Sink 0.4 1.4 1.0 1.0 1.0 0.4 >50 1.70 1.070
BUFFERED EXTERNAL REFERENCE (REFIN driven externally, VREFIN = 2.048V, VREFP, VREFN, and VCOM are generated internally) REFIN Input Voltage REFP Output Voltage REFN Output Voltage COM Output Voltage Differential Reference Output Voltage Differential Reference Temperature Coefficient Maximum REFP Current Maximum REFN Current Maximum COM Current REFIN Input Resistance V V V V V ppm/C mA mA mA M
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3
40Msps, 12-Bit ADC MAX1206
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CREFOUT = 0.1F, CL 5pF at digital outputs, VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 40MHz (50% duty cycle), CREFP = CREFN = 0.1F to GND, 1F in parallel with 10F between REFP and REFN, CCOM = 0.1F in parallel with 2.2F to GND, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER COM Input Voltage REFP Input Voltage REFN Input Voltage Differential Reference Input Voltage REFP Sink Current REFN Source Current COM Sink Current REFP, REFN, Capacitance COM Capacitance CLOCK INPUTS (CLKP, CLKN) Single-Ended Input High Threshold Single-Ended Input Low Threshold Differential Input Voltage Swing Differential Input Common-Mode Voltage Minimum Clock Duty Cycle Maximum Clock Duty Cycle Input Resistance Input Capacitance DIGITAL INPUTS (CLKTYP, G/T, PD) Input High Threshold Input Low Threshold Input Leakage Current Input Capacitance CDIN VIH VIL VIH = OVDD VIL = 0 5 0.8 x OVDD 0.2 x OVDD 5 5 V V A pF RCLK CCLK VIH VIL CLKTYP = GND, CLKN = GND CLKTYP = GND, CLKN = GND CLKTYP = high CLKTYP = high DCE = OVDD DCE = GND DCE = OVDD DCE = GND Figure 4 1.4 VDD / 2 20 45 80 60 5 2 0.8 x VDD 0.2 x VDD V V VP-P V % % k pF VREF IREFP IREFN ICOM SYMBOL VCOM VDD / 2 VREFP - VCOM VREFN - VCOM VREF = VREFP - VREFN VREFP = 2.162V VREFN = 1.138V CONDITIONS MIN TYP 1.65 0.512 -0.512 1.024 1.1 1.1 0.3 13 6 MAX UNITS V V V V mA mA mA pF pF
UNBUFFERED EXTERNAL REFERENCE (REFIN = GND, VREFP, VREFN, and VCOM are applied externally)
4
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40Msps, 12-Bit ADC
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CREFOUT = 0.1F, CL 5pF at digital outputs, VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 40MHz (50% duty cycle), CREFP = CREFN = 0.1F to GND, 1F in parallel with 10F between REFP and REFN, CCOM = 0.1F in parallel with 2.2F to GND, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER SYMBOL CONDITIONS D0-D11, DOR, ISINK = 200A DAV, ISINK = 600A D0-D11, DOR, ISOURCE = 200A Output-Voltage High VOH DAV, ISOURCE = 600A Tri-State Leakage Current D11-D0, DOR Tri-State Output Capacitance DAV Tri-State Output Capacitance POWER REQUIREMENTS Analog Supply Voltage Digital Output Supply Voltage VDD OVDD Normal operating mode, fIN = 20MHz at -0.5dBFS, CLKTYP = GND, single-ended clock Analog Supply Current IVDD Normal operating mode, fIN = 20MHz at -0.5dBFS, CLKTYP = OVDD, differential clock Power-down mode; clock idle, PD = OVDD Normal operating mode, fIN = 20MHz at -0.5dBFS, CLKTYP = GND, single-ended clock Analog Power Dissipation PDISS Normal operating mode, fIN = 20MHz at -0.5dBFS, CLKTYP = OVDD, differential clock Power-down mode, clock idle, PD = OVDD 3.0 1.7 3.3 2.0 3.6 VDD + 0.3V V V ILEAK COUT CDAV (Note 4) (Note 4) (Note 4) 3 6 OVDD - 0.2 V OVDD - 0.2 5 A pF pF MIN TYP MAX 0.2 0.2 UNITS DIGITAL OUTPUTS (D0-D11, DAV, DOR) Output-Voltage Low VOL V
MAX1206
54.7
60.1
66
mA
0.045
181
198
218
mW
0.15
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5
40Msps, 12-Bit ADC MAX1206
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CREFOUT = 0.1F, CL 5pF at digital outputs, VIN = -0.5dBFS, CLKTYP = high, DCE = high, PD = low, G/T = low, fCLK = 40MHz (50% duty cycle), CREFP = CREFN = 0.1F to GND, 1F in parallel with 10F between REFP and REFN, CCOM = 0.1F in parallel with 2.2F to GND, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER SYMBOL CONDITIONS Normal operating mode, fIN = 20MHz at -0.5dBFS, OVDD = 2.0V, CL 5pF Power-down mode; clock idle, PD = OVDD TIMING CHARACTERISTICS (Figure 5) Clock Pulse-Width High Clock Pulse-Width Low Data Valid Delay Data Setup Time Before Rising Edge of DAV Data Hold Time After Rising Edge of DAV Wake-Up Time from Power-Down tCH tCL tDAV tSETUP tHOLD tWAKE CL = 5pF (Note 5) CL = 5pF (Notes 3, 5) CL = 5pF (Notes 3, 5) VREFIN = 2.048V 13.9 10.7 10 12.5 12.5 6.4 ns ns ns ns ns ms MIN TYP 6.1 MAX UNITS mA
Digital Output Supply Current
IOVDD
6
A
Note 1: Note 2: Note 3: Note 4: Note 5:
Specifications +25C guaranteed by production test, <+25C guaranteed by design and characterization. Specifications guaranteed by design and characterization. Devices tested for performance during production test. Guaranteed by design and characterization. During power-down, D11-D0, DOR, and DAV are high impedance. Digital outputs settle to VIH or VIL.
6
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40Msps, 12-Bit ADC MAX1206
Typical Operating Characteristics
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CREFOUT = 0.1F, CL 5pF at digital outputs, VIN = -0.5dBFS differential input, DCE = high, CLKTYP = high, PD = low, G/T = low, fCLK = 40MHz (50% duty cycle), CREFP = CREFN = 0.1F to GND, 1F in parallel with 10F between REFP and REFN, CCOM = 0.1F in parallel with 2.2F to GND, TA = +25C, unless otherwise noted.)
SINGLE-TONE FFT PLOT (8192-POINT DATA RECORD)
MAX1206 toc01
SINGLE-TONE FFT PLOT (8192-POINT DATA RECORD)
MAX1206 toc02
SINGLE-TONE FFT PLOT (8192-POINT DATA RECORD)
-10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 -110 HD4 HD5 HD2 fCLK = 40.0004Msps fIN = 70.0837MHz AIN = -0.48dBFS SNR = 68.22dBc SINAD = 68.16dBc THD = -86.9dBc SFDR = 90.1dBc
MAX1206 toc03
0 -10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 -110 0 4 8 HD5
AMPLITUDE (dBFS)
fCLK = 40.0004Msps fIN = 9.8975MHz AIN = -0.5dBFS SNR = 68.72dBc SINAD = 68.67dBc THD = -88.4dBc SFDR = 92.18dBc
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110
fCLK = 40.0004Msps fIN = 19.9074MHz AIN = -0.5304dBFS SNR = 68.71dBc SINAD = 68.67dBc THD = -89.7dBc SFDR = 92.4dBc
0
HD3
HD2
HD2
HD3
12
16
20
0
4
8
12
16
20
0
4
8
12
16
20
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
TWO-TONE FFT PLOT (16,384-POINT DATA RECORD)
MAX1206 toc04
TWO-TONE FFT PLOT (16,384-POINT DATA RECORD)
-10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 -110 fIN2 fCLK = 40.0004Msps fIN1 = 69.0022MHz AIN1 = -7.0dBFS fIN2 = 71.0041MHz AIN2 = -7.0dBFS SNR = 64.01dBc SINAD = 64.00dBc SFDRTT = 88.44dBc IMD = -85.56dB IM3 = -88.65dBc fIN1
MAX1206 toc05 MAX1206 toc07
0 -10 -20 AMPLITUDE (dBFS) -30 -40 -50 -60 -70 -80 -90 -100 -110 0 4 8 fIN2 fIN1
0
fCLK = 40.0004Msps fIN1 = 44.0019MHz AIN1 = -7.0dBFS fIN2 = 46.0039MHz AIN2 = -7.0dBFS SNR = 64.64dBc SINAD = 64.63dBc SFDRTT = 88.3dBc IMD = -85.21dB IM3 = -93.89dBc
12
16
20
0
4
8
12
16
20
FREQUENCY (MHz)
FREQUENCY (MHz)
INTEGRAL NONLINEARITY
0.8 0.6 0.4 DNL (LSB) INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 DIGITAL OUTPUT CODE
MAX1206 toc06
DIFFERENTIAL NONLINEARITY
0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 512 1024 1536 2048 2560 3072 3584 4096 DIGITAL OUTPUT CODE
1.0
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7
40Msps, 12-Bit ADC MAX1206
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CREFOUT = 0.1F, CL 5pF at digital outputs, VIN = -0.5dBFS differential input, DCE = high, CLKTYP = high, PD = low, G/T = low, fCLK = 40MHz (50% duty cycle), CREFP = CREFN = 0.1F to GND, 1F in parallel with 10F between REFP and REFN, CCOM = 0.1F in parallel with 2.2F to GND, TA = +25C, unless otherwise noted.)
SIGNAL-TO-NOISE RATIO vs. SAMPLING RATE
MAX1206 toc08
SIGNAL-TO-NOISE + DISTORTION vs. SAMPLING RATE
69 68 67 SINAD (dB) 66 65 64 63 62 61 60 fIN = 19.9MHz
MAX1206 toc09
70 69 68 67 SNR (dB) 66 65 64 63 62 61 60
70
fIN = 19.9MHz
10
15
20
25 fCLK (MHz)
30
35
40
10
15
20
25 fCLK (MHz)
30
35
40
TOTAL HARMONIC DISTORTION vs. SAMPLING RATE
MAX1206 toc10
SPURIOUS-FREE DYNAMIC RANGE vs. SAMPLING RATE
fIN = 19.9MHz 95 90 SFDR (dBc) 85 80 75 70 65
MAX1206 toc11
-60 -65 -70 THD (dBc) -75 -80 -85 -90 -95 -100
fIN = 19.9MHz
100
10
15
20
25 fCLK (MHz)
30
35
40
60 10 15 20 25 fCLK (MHz) 30 35 40
8
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40Msps, 12-Bit ADC MAX1206
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CREFOUT = 0.1F, CL 5pF at digital outputs, VIN = -0.5dBFS differential input, DCE = high, CLKTYP = high, PD = low, G/T = low, fCLK = 40MHz (50% duty cycle), CREFP = CREFN = 0.1F to GND, 1F in parallel with 10F between REFP and REFN, CCOM = 0.1F in parallel with 2.2F to GND, TA = +25C, unless otherwise noted.)
SIGNAL-TO-NOISE RATIO vs. SAMPLING RATE
MAX1206 toc12
SIGNAL-TO-NOISE + DISTORTION vs. SAMPLING RATE
69 68 67 SINAD (dB) 66 65 64 63 62 61 60 fIN = 70.1MHz
MAX1206 toc13
70 69 68 67 SNR (dB) 66 65 64 63 62 61 60
70
fIN = 70.1MHz
10
15
20
25 fCLK (MHz)
30
35
40
10
15
20
25 fCLK (MHz)
30
35
40
TOTAL HARMONIC DISTORTION vs. SAMPLING RATE
MAX1206 toc14
SPURIOUS-FREE DYNAMIC RANGE vs. SAMPLING RATE
fIN = 70.1MHz 95 90 SFDR (dBc) 85 80 75 70 65
MAX1206 toc15
-60 -65 -70 THD (dBc) -75 -80 -85 -90 -95 -100
fIN = 70.1MHz
100
10
15
20
25 fCLK (MHz)
30
35
40
60 10 15 20 25 fCLK (MHz) 30 35 40
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9
40Msps, 12-Bit ADC MAX1206
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CREFOUT = 0.1F, CL 5pF at digital outputs, VIN = -0.5dBFS differential input, DCE = high, CLKTYP = high, PD = low, G/T = low, fCLK = 40MHz (50% duty cycle), CREFP = CREFN = 0.1F to GND, 1F in parallel with 10F between REFP and REFN, CCOM = 0.1F in parallel with 2.2F to GND, TA = +25C, unless otherwise noted.)
SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY
MAX1206 toc16
SIGNAL-TO-NOISE + DISTORTION vs. ANALOG INPUT FREQUENCY
69 68 67 SINAD (dB) 66 65 64 63 62 61 60
MAX1206 toc17
70 69 68 67 SNR (dB) 66 65 64 63 62 61 60 0 25 50 75 100
70
125
0
25
50
75
100
125
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
TOTAL HARMONIC DISTORTION vs. ANALOG INPUT FREQUENCY
MAX1206 toc18
SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY
95 90 SFDR (dBc) 85 80 75 70 65
MAX1206 toc19
-60 -65 -70 THD (dBc) -75 -80 -85 -90 -95 -100 0 25 50 75 100
100
125
60 0 25 50 75 100 125 ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
10
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40Msps, 12-Bit ADC MAX1206
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CREFOUT = 0.1F, CL 5pF at digital outputs, VIN = -0.5dBFS differential input, DCE = high, CLKTYP = high, PD = low, G/T = low, fCLK = 40MHz (50% duty cycle), CREFP = CREFN = 0.1F to GND, 1F in parallel with 10F between REFP and REFN, CCOM = 0.1F in parallel with 2.2F to GND, TA = +25C, unless otherwise noted.)
SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT POWER
MAX1206 toc20
SIGNAL-TO-NOISE + DISTORTION vs. ANALOG INPUT POWER
fIN = 19.900286MHz 70 65 SINAD (dB) 60 55 50 45 40 35
MAX1206 toc21
75 70 65 SNR (dB) 60 55 50 45 40 35
fIN = 19.900286MHz
75
-30
-25
-20
-15
-10
-5
0
-30
-25
-20
-15
-10
-5
0
ANALOG INPUT POWER (dBFS)
ANALOG INPUT POWER (dBFS)
TOTAL HARMONIC DISTORTION vs. ANALOG INPUT POWER
MAX1206 toc22
SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT POWER
fIN = 19.900286MHz 90 85 SFDR (dBc) 80 75 70 65 60
MAX1206 toc23
-55 -60 -65 THD (dBc) -70 -75 -80 -85 -90 -95 -30 -25 -20 -15
fIN = 19.900286MHz
95
-10
-5
0
55 -30 -25 -20 -15 -10 -5 0 ANALOG INPUT POWER (dBFS)
ANALOG INPUT POWER (dBFS)
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11
40Msps, 12-Bit ADC MAX1206
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CREFOUT = 0.1F, CL 5pF at digital outputs, VIN = -0.5dBFS differential input, DCE = high, CLKTYP = high, PD = low, G/T = low, fCLK = 40MHz (50% duty cycle), CREFP = CREFN = 0.1F to GND, 1F in parallel with 10F between REFP and REFN, CCOM = 0.1F in parallel with 2.2F to GND, TA = +25C, unless otherwise noted.)
SIGNAL-TO-NOISE RATIO vs. CLOCK DUTY CYCLE
MAX1206 toc24
SIGNAL-TO-NOISE + DISTORTION vs. CLOCK DUTY CYCLE
70 69 68 SINAD (dB) SINGLE-ENDED CLOCK fIN = 19.9002858MHz
MAX1206 toc25
71 70 69 68 SNR (dB) 67 66 65 64 63 62 61
SINGLE-ENDED CLOCK fIN = 19.9002858MHz
71
DCE = HIGH
67 66 65 64 63 62 61
DCE = HIGH
DCE = LOW
DCE = LOW
20
30
40
50
60
70
80
20
30
40
50
60
70
80
CLOCK DUTY CYCLE (%)
CLOCK DUTY CYCLE (%)
TOTAL HARMONIC DISTORTION vs. CLOCK DUTY CYCLE
MAX1206 toc26
SPURIOUS-FREE DYNAMIC RANGE vs. CLOCK DUTY CYCLE
SINGLE-ENDED CLOCK fIN = 19.9002858MHz
MAX1206 toc27
-65 -70 -75 THD (dBc) -80 -85 -90 DCE = HIGH -95 -100 20 30 40 50 60 70 SINGLE-ENDED CLOCK fIN = 19.9002858MHz DCE = LOW
100 95 90 SFDR (dBc) 85 80
DCE = HIGH DCE = LOW
75 70 65 80 20 30 40 50 60 70 80 CLOCK DUTY CYCLE (%) CLOCK DUTY CYCLE (%)
12
______________________________________________________________________________________
40Msps, 12-Bit ADC MAX1206
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CREFOUT = 0.1F, CL 5pF at digital outputs, VIN = -0.5dBFS differential input, DCE = high, CLKTYP = high, PD = low, G/T = low, fCLK = 40MHz (50% duty cycle), CREFP = CREFN = 0.1F to GND, 1F in parallel with 10F between REFP and REFN, CCOM = 0.1F in parallel with 2.2F to GND, TA = +25C, unless otherwise noted.)
SIGNAL-TO-NOISE RATIO vs. ANALOG POWER-INPUT VOLTAGE
MAX1206 toc28
SIGNAL-TO-NOISE + DISTORTION vs. ANALOG POWER-INPUT VOLTAGE
69 68 67 SINAD (dB) 66 65 64 63 62 61 60 fIN = 19.9MHz
MAX1206 toc29
70 69 68 67 SNR (dB) 66 65 64 63 62 61 60
fIN = 19.9MHz
70
2.7
3.0 VDD (V)
3.3
3.6
2.7
3.0 VDD (V)
3.3
3.6
TOTAL HARMONIC DISTORTION vs. ANALOG POWER-INPUT VOLTAGE
MAX1206 toc30
SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG POWER-INPUT VOLTAGE
fIN = 19.9MHz 95 90 SFDR (dBc) 85 80 75 70 65 60
MAX1206 toc31a
-60 -65 -70 THD (dBc) -75 -80 -85 -90 -95 -100
fIN = 19.9MHz
100
2.7
3.0 VDD (V)
3.3
3.6
2.7
3.0 VDD (V)
3.3
3.6
ANALOG POWER DISSIPATION vs. ANALOG POWER-INPUT VOLTAGE
fIN = 19.9MHz
MAX1206 toc31b
240 220 200 PDISS (mW) 180 160 140 120 2.7
DIFFERENTIAL CLOCK
SINGLE-ENDED CLOCK
3.0 VDD (V)
3.3
3.6
______________________________________________________________________________________
13
40Msps, 12-Bit ADC MAX1206
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CREFOUT = 0.1F, CL 5pF at digital outputs, VIN = -0.5dBFS differential input, DCE = high, CLKTYP = high, PD = low, G/T = low, fCLK = 40MHz (50% duty cycle), CREFP = CREFN = 0.1F to GND, 1F in parallel with 10F between REFP and REFN, CCOM = 0.1F in parallel with 2.2F to GND, TA = +25C, unless otherwise noted.)
SIGNAL-TO-NOISE RATIO vs. TEMPERATURE
MAX1206 toc32
SIGNAL-TO-NOISE + DISTORTION vs. TEMPERATURE
69 68 67 SINAD (dB) 66 65 64 63 62 61 60 fIN = 19.9MHz
MAX1206 toc33
70 69 68 67 SNR (dB) 66 65 64 63 62 61 60 -40 -15 10 35 60 fIN = 19.9MHz
70
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
TOTAL HARMONIC DISTORTION vs. TEMPERATURE
MAX1206 toc34
SPURIOUS-FREE DYNAMIC RANGE vs. TEMPERATURE
fIN = 19.9MHz
MAX1206 toc35
-70 -75 -80 -85 -90 -95 -100 -40
fIN = 19.9MHz
100 95 90 SFDR (dBc) 85 80 75 70
THD (dBc)
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
14
______________________________________________________________________________________
40Msps, 12-Bit ADC MAX1206
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CREFOUT = 0.1F, CL 5pF at digital outputs, VIN = -0.5dBFS differential input, DCE = high, CLKTYP = high, PD = low, G/T = low, fCLK = 40MHz (50% duty cycle), CREFP = CREFN = 0.1F to GND, 1F in parallel with 10F between REFP and REFN, CCOM = 0.1F in parallel with 2.2F to GND, TA = +25C, unless otherwise noted.)
OFFSET ERROR vs. TEMPERATURE
MAX1206 toc36
GAIN ERROR vs. TEMPERATURE
0.9 0.8 GAIN ERROR (%FR) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 VREFIN = 2.048V
MAX1206 toc37
-0.12 -0.14 OFFSET ERROR (%FS) -0.16 -0.18 -0.20 -0.22 -0.24 -0.26 -0.28
1.0
VREFIN = 2.048V
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
Pin Description
PIN 1 2 3 4, 7, 16, 35 5 6 8 NAME REFP REFN COM GND INP INN DCE FUNCTION Positive Reference I/O. Conversion range is (VREFP - VREFN). Bypass REFP to GND with a 0.1F capacitor. Connect a 1F capacitor in parallel with a 10F capacitor between REFP and REFN. Negative Reference I/O. Conversion range is (VREFP - VREFN). Bypass REFN to GND with a 0.1F capacitor. Connect a 1F capacitor in parallel with a 10F capacitor between REFP and REFN. Common-Mode Voltage I/O. Bypass COM to GND with a 2.2F capacitor in parallel with a 0.1F capacitor. Ground. Connect all ground pins and the EP together. Positive Analog Input. For single-ended input operation, connect signal source to INP and connect INN to COM. For differential operation, connect the input signal between INP and INN. Negative Analog Input. For single-ended input operation, connect INN to COM. For differential operation, connect the input signal between INP and INN. Duty-Cycle Equalizer Input. Connect DCE low (GND) to disable the internal duty-cycle equalizer. Connect DCE high (OVDD or DVDD) to enable the internal duty-cycle equalizer. Negative Clock Input. In differential clock input mode (CLKTYP = OVDD or VDD), connect the clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the clock signal to CLKP and tie CLKN to GND. Positive Clock Input. In differential clock input mode (CLKTYP = OVDD or VDD), connect the differential clock signal between CLKP and CLKN. In single-ended clock mode (CLKTYP = GND), apply the singleended clock signal to CLKP and connect CLKN to GND.
9
CLKN
10
CLKP
______________________________________________________________________________________
15
40Msps, 12-Bit ADC MAX1206
Pin Description (continued)
PIN 11 12-15, 36 17, 34 NAME CLKTYP VDD OVDD FUNCTION Clock Type Definition Input. Connect CLKTYP to GND to define the single-ended clock input. Connect CLKTYP to OVDD or VDD to define the differential clock input. Analog Power Input. Connect VDD to a 3.0V to 3.6V power supply. Bypass VDD to GND with a parallel capacitor combination of 2.2F and 0.1F. Connect all VDD pins to the same potential. Output Driver Power Input. Connect OVDD to a 1.7V to VDD power supply. Bypass OVDD to GND with a parallel capacitor combination of 2.2F and 0.1F. Data Out-of-Range Indicator. The DOR digital output indicates when the analog input voltage is out of range. When DOR is high, the analog input is beyond its full-scale range. When DOR is low, the analog input is within its full-scale range. CMOS Digital Output, Bit 11 (MSB) CMOS Digital Output, Bit 10 CMOS Digital Output, Bit 9 CMOS Digital Output, Bit 8 CMOS Digital Output, Bit 7 CMOS Digital Output, Bit 6 CMOS Digital Output, Bit 5 CMOS Digital Output, Bit 4 CMOS Digital Output, Bit 3 CMOS Digital Output, Bit 2 CMOS Digital Output, Bit 1 CMOS Digital Output, Bit 0 (LSB) Internally Connected. Leave I.C. unconnected. Data Valid Output. The DAV is a single-ended version of the input clock that is compensated to correct for any input clock duty-cycle variations. The MAX1211 evaluation kit (MAX1211EVKIT) utilizes DAV to latch data (D0-D11) into external back-end digital circuitry. Power-Down Input. Force PD high for power-down mode. Force PD low for normal operation. Internal Reference Voltage Output. For internal reference operation, connect REFOUT directly to REFIN or use a resistive-divider from REFOUT to set the voltage at REFIN. Bypass REFOUT to GND with a 0.1F capacitor. Reference Input. VREFIN = 2 x (VREFP - VREFN). Bypass REFIN to GND with a 0.1F capacitor. Output Format Select Input. Connect G/T to GND for the two's complement digital output format. Connect G/T to OVDD or VDD for the Gray code digital output format. Exposed Paddle. EP is internally connected to GND. Externally connect EP to GND to achieve specified performance.
18 19 20 21 22 23 24 25 26 27 28 29 30 31, 32 33 37 38 39 40 --
DOR D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 I.C. DAV PD REFOUT REFIN G/T EP
16
______________________________________________________________________________________
40Msps, 12-Bit ADC
Detailed Description
The MAX1206 uses a 10-stage, fully differential, pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half clock cycle. From input to output, the total clock-cycle latency is 8.5 clock cycles. Each pipeline converter stage converts its input voltage into a digital output code. At every stage, except the last, the error between the input voltage and the digital output code is multiplied and passed along to the next pipeline stage. Digital error correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing codes. Figure 2 shows the MAX1206 functional diagram. C2a and C2b. These values are then presented to the first-stage quantizers and isolate the pipelines from the fast-changing inputs. The wide input-bandwidth T/H amplifier allows the MAX1206 to track and sample/hold analog inputs of high frequencies well beyond Nyquist. Analog input INP to INN can be driven either differentially or single ended. For differential inputs, balance the input impedance of INP and INN and set the common-mode voltage to midsupply (VDD / 2) for optimum performance.
MAX1206
CLKP CLKN DCE CLKTYP
CLOCK GENERATOR AND DUTY-CYCLE EQUALIZER
MAX1206
VDD GND
OVDD 12-BIT PIPELINE ADC OUTPUT DRIVERS D0-D11 DAV DOR G/T
Input Track-and-Hold (T/H) Circuit
Figure 3 displays a simplified functional diagram of the input T/H circuits. In track mode, switches S1, S2a, S2b, S4a, S4b, S5a, and S5b are closed. The fully differential circuits sample the input signals onto the two capacitors (C2a and C2b) through switches S4a and S4b. S2a and S2b set the common mode for the operational transconductance amplifier (OTA), and open simultaneously with S1, sampling the input waveform. Switches S4a, S4b, S5a, and S5b are then opened before switches S3a and S3b connect capacitors C1a and C1b to the output of the amplifier and switch S4c is closed. The resulting differential voltages are held on capacitors C2a and C2b. The amplifiers charge capacitors C1a and C1b to the same values originally held on
INP T/H INN DEC
REFOUT REFIN REFP COM REFN
REFERENCE SYSTEM
POWER CONTROL AND BIAS CIRCUITS
PD
Figure 2. Functional Diagram
SWITCHES SHOWN IN TRACK MODE INTERNAL BIAS CML S5a S3a
MAX1206
T/H
+
S2a
C1a
x2
VDD S4a INP C2a
FLASH ADC DAC
OUT S4c S1 OTA OUT INN S4b
1.5 BITS INP T/H INN
STAGE 1 GAIN OF 8 4 BITS
STAGE 2 GAIN OF 2 1.5 BITS
STAGE 9 GAIN OF 2 1.5 BITS
STAGE 10 END OF PIPE 1 BIT
C2b
C1b S3b S2b S5b CML
GND
DIGITAL ERROR CORRECTION D0-D11 INTERNAL BIAS
Figure 1. Pipeline Architecture--Stage Blocks
Figure 3. Internal T/H Circuit 17
______________________________________________________________________________________
40Msps, 12-Bit ADC MAX1206
Table 1. Reference Modes
VREFIN 35% VREFOUT to 100% VREFOUT 0.7V to 2.3V <0.5V REFERENCE MODE Internal reference mode. REFIN is driven by REFOUT either through a direct short or a resistive divider. VCOM = VDD / 2, VREFP = VDD / 2 + VREFIN / 4, and VREFN = VDD / 2 - VREFIN / 4. Buffered external reference mode. An external 0.7V to 2.3V reference voltage is applied to REFIN. VCOM = VDD / 2, VREFP = VDD / 2 + VREFIN / 4, and VREFN = VDD / 2 - VREFIN / 4. Unbuffered external reference mode. REFP, REFN, and COM are driven by external reference sources. VREF is the difference between the externally applied VREFP and VREFN.
Reference Output (REFOUT)
An internal bandgap reference is the basis for all the internal voltages and bias currents used in the MAX1206. The power-down logic input (PD) enables and disables the reference circuit. REFOUT has approximately 17k to GND when the MAX1206 is in power-down. The reference circuit requires 10ms to power up and settle when power is applied to the MAX1206 or when PD transitions from high to low. The internal bandgap reference and buffer generate REFOUT to be 2.048V with a +100ppm/C temperature coefficient. Connect an external 0.1F bypass capacitor from REFOUT to GND for stability. REFOUT sources up to 1.4mA and sinks up to 100A for external circuits with a load regulation of 35mV/mA. Short-circuit protection limits IREFOUT to a 2.1mA source current when shorted to GND and a 240A sink current when shorted to VDD.
with VCOM = VDD / 2, VREFP = VDD / 2 + VREFIN / 4, and VREFN = VDD / 2 - VREFIN / 4. To operate the MAX1206 in unbuffered external reference mode, connect REFIN to GND. Connecting REFIN to GND deactivates the on-chip reference buffers for COM, REFP, and REFN. With their buffers deactivated, COM, REFP, and REFN inputs must be driven through separate, external reference sources. Drive V COM to V DD / 2 5%, and drive REFP and REFN such that VCOM = (VREFP + VREFN) / 2. The analog input range is (VREFP - VREFN). All three modes of reference operation require the same bypass capacitor combination. Bypass COM with a 0.1F capacitor in parallel with a 2.2F capacitor to GND. Bypass REFP and REFN each with a 0.1F capacitor to GND. Bypass REFP to REFN with a 1F capacitor in parallel with a 10F capacitor. Place the 1F capacitor as close to the device as possible. Bypass REFIN and REFOUT to GND with a 0.1F capacitor. For detailed circuit suggestions, see Figures 12 and 13.
Analog Inputs and Reference Configurations
The MAX1206 full-scale analog input range is VREF with a common-mode input range of V DD / 2 0.8V. VREF is the difference between VREFP and VREFN. The MAX1206 provides three modes of reference operation. The voltage at REFIN (VREFIN) sets the reference operation mode (Table 1). To operate the MAX1206 with the internal reference, connect REFOUT to REFIN either with a direct short or through a resistive-divider. In this mode, COM, REFP, and REFN are low-impedance outputs with VCOM = VDD / 2, VREFP = VDD / 2 + VREFIN / 4, and VREFN = VDD / 2 VREFIN / 4. The REFIN input impedance is very large (>50M). When driving REFIN through a resistive-divider, use resistances 10k to avoid loading REFOUT. Buffered external reference mode is virtually identical to internal reference mode except that the reference source is derived from an external reference and not the MAX1206 REFOUT. In buffered external reference mode, apply a stable 0.7V to 2.3V source at REFIN. COM, REFP, and REFN are low-impedance outputs
18
Clock Input and Clock Control Lines (CLKP, CLKN, CLKTYP, DCE)
The MAX1206 accepts both differential and singleended clock inputs. For single-ended clock input operation, connect CLKTYP to GND, CLKN to GND, and drive CLKP with the external single-ended clock signal. For differential clock input operation, connect CLKTYP to OVDD or VDD and drive CLKP and CLKN with the external differential clock signal. To reduce clock jitter, the external single-ended clock must have sharp falling edges. Consider the clock input as an analog input and route it away from any other analog inputs and digital signal lines. CLKP and CLKN are high impedance when the MAX1206 is powered down (Figure 4). Low clock jitter is required for the specified SNR performance of the MAX1206. Analog input sampling occurs on the falling edge of the clock signal, requiring this
______________________________________________________________________________________
40Msps, 12-Bit ADC
edge to have the lowest possible jitter. Jitter limits the maximum SNR performance of any ADC according to the following relationship: 1 SNR = 20 x log 2 x x fIN x t J where fIN represents the analog input frequency and tJ is the total system clock jitter. Clock jitter is especially critical for undersampling applications. For example, assuming that clock jitter is the only noise source, to obtain the specified 68.5dB of SNR with an input frequency of 20MHz, the system must have less than 3ps of clock jitter.
CLKP 10k S2H 10k DUTYCYCLE EQUALIZER
MAX1206
VDD S1H
MAX1206
10k
S1L CLKN
Clock Duty-Cycle Equalizer (DCE)
The MAX1206 clock duty-cycle equalizer allows for a wide 20% to 80% clock duty cycle when enabled (DCE = OV DD or V DD ). When disabled (DCE = GND), the MAX1206 accepts a narrow 45% to 60% clock duty cycle. The clock duty-cycle equalizer uses a delay-locked loop to create internal timing signals that are duty-cycle independent. Due to this delay-locked loop, the MAX1206 requires approximately 100 clock cycles to acquire and lock to new clock frequencies. Disabling the clock duty-cycle equalizer reduces the analog supply current by 1.5mA.
S2L GND
10k SWITCHES S1_ AND S2_ ARE OPEN DURING POWER-DOWN, MAKING CLKP AND CLKN HIGH IMPEDANCE. SWITCHES S2_ ARE OPEN IN SINGLE-ENDED CLOCK MODE.
Figure 4. Simplified Clock Input Circuit
System Timing Requirements
Figure 5 shows the relationship between the clock, analog inputs, DAV indicator, DOR indicator, and the resulting output data. The analog input is sampled on the falling edge of the clock signal and the resulting data appears at the digital outputs 8.5 clock cycles later. The DAV indicator is synchronized with the digital output and optimized for use in latching data into digital back-end circuitry. Alternatively, digital back-end circuitry can be latched with the falling edge of the clock. Data Valid Output (DAV) DAV is a single-ended version of the input clock (CLKP). The output data changes on the falling edge of DAV, and DAV rises once the output data is valid. The state of the duty-cycle equalizer input (DCE) changes the waveform at DAV. With the duty-cycle equalizer disabled (DCE low), the DAV signal is the inverse of the signal at CLKP delayed by 6.4ns. With the duty-cycle equalizer enabled (DCE high), the DAV signal has a fixed pulse width that is independent of CLKP. In either case, with DCE high or low, output data at D0-D11 and DOR are valid from 13.9ns before the
rising edge of DAV to 10.7ns after the rising edge of DAV, and the rising edge of DAV is synchronized to have a 6.4ns delay from the falling edge of CLKP. DAV is high impedance when the MAX1206 is in powerdown (PD = high). DAV is capable of sinking and sourcing 600A and has three times the drive strength of D0-D11 and DOR. DAV is typically used to latch the MAX1206 output data into an external back-end digital circuit. Keep the capacitive load on DAV as low as possible (<25pF) to avoid large digital currents feeding back into the analog portion of the MAX1206 and degrading its dynamic performance. An external buffer on DAV isolates it from heavy capacitive loads. Refer to the MAX1211 evaluation kit schematic for an example of DAV driving back-end digital circuitry through an external buffer. Data Out-of-Range Indicator (DOR) The DOR digital output indicates when the analog input voltage is out of range. When DOR is high, the analog input is out of range. When DOR is low, the analog input is within range. The valid differential input range is from (VREFP - VREFN) to (VREFN - VREFP). Signals outside this valid differential range cause DOR to assert high as shown in Table 2.
______________________________________________________________________________________
19
40Msps, 12-Bit ADC MAX1206
Table 2. Output Codes vs. Input Voltage
GRAY CODE OUTPUT CODE T (G/T = 1) DECIMAL HEXADECIMAL EQUIVALENT EQUIVALENT DOR OF OF D11 D0 D11 D0 (CODE10) TWO'S COMPLEMENT OUTPUT CODE T (G/T = 0) DECIMAL HEXADECIMAL EQUIVALENT EQUIVALENT DOR OF OF D11 D0 D11 D0 (CODE10)
(
VINP - VINN VREFP = 2.162V VREFN = 1.138V
)
BINARY D11 D0
BINARY D11 D0
1000 0000 0000 1000 0000 0000 1000 0000 0001 1100 0000 0011 1100 0000 0001 1100 0000 0000 0100 0000 0000 0100 0000 0001 0000 0000 0001 0000 0000 0000 0000 0000 0000
1 0 0 0 0 0 0 0 0 0 1
0x800 0x800 0x801 0xC03 0xC01 0xC00 0x400 0x401 0x001 0x000 0x000
+4095 +4095 +4094 +2050 +2049 +2048 +2047 +2046 +1 0 0
0111 1111 1111 0111 1111 1111 0111 1111 1110 0000 0000 0010 0000 0000 0001 0000 0000 0000 1111 1111 1111 1111 1111 1110 1000 0000 0001 1000 0000 0000 1000 0000 0000
1 0 0 0 0 0 0 0 0 0 1
0x7FF 0x7FF 0x7FE 0x002 0x001 0x000 0xFFF 0xFFE 0x801 0x800 0x800
+2047 +2047 +2046 +2 +1 0 -1 -2 -2047 -2048 -2048
>+1.0235V (DATA OUT OF RANGE) +1.0235V +1.0230V +0.0010V +0.0005V +0.0000V -0.0005V -0.0010V -1.0235V -1.0240V <-1.0240V (DATA OUT OF RANGE)
DIFFERENTIAL ANALOG INPUT (INP - INN) (VREFP - VREFN) N+3 N-3 N-2 N-1 N N+1 N+2
N+4
N+5 N+6 N+7 N+8 N+9
(VREFN - VREFP)
tAD CLKN CLKP tDAV DAV tSETUP D0-D11 tHOLD N-3 8.5 CLOCK CYCLE DATA LATENCY DOR N-2 N-1 N N+1 N+ 2 N+3 N+4 N+5 tSETUP N+6 N+7 N+8 N+9 tHOLD tCL tCH
Figure 5. System Timing Diagram
20
______________________________________________________________________________________
40Msps, 12-Bit ADC
DOR is synchronized with DAV and transitions along with output data D0-D11. There is an 8.5 clock-cycle latency in the DOR function just as with the output data (Figure 5). DOR is high impedance when the MAX1206 is in power-down (PD = high). DOR enters a high-impedance state within 10ns of the rising edge of PD and becomes active within 10ns of PD's falling edge. Digital Output Data (D0-D11), Output Format (G/T) The MAX1206 provides a 12-bit, parallel, tri-state output bus. D0-D11 and DOR update on the falling edge of DAV and are valid on the rising edge of DAV. The MAX1206 output data format is either Gray code or two's complement, depending on the logic input G/T. With G/T high, the output data format is Gray code. With G/T low, the output data format is two's complement. See Figure 8 for a binary-to-Gray and Gray-tobinary code-conversion example. The following equations, Table 2, Figure 6, and Figure 8 define the relationship between the digital output and the analog input: CODE10 - 2048 VINP - VINN = (VREFP - VREFN ) x 2 x 4096 for Gray code (G/T = 1).
1 LSB =
MAX1206
1 LSB =
2 x VREF 4096 VREF
VREF = VREFP - VREFN VREF
TWO'S COMPLEMENT OUTPUT CODE (LSB)
0x7FF 0x7FE 0x7FD
0x001 0x000 0xFFF
0x803 0x802 0x801 0x800
-2047 -2045 -1 0 +1 +2045 +2047
DIFFERENTIAL INPUT VOLTAGE (LSB)
Figure 6. Two's Complement Transfer Function (G/T = 0)
CODE10 VINP - VINN = (VREFP - VREFN ) x 2 x 4096 for two's complement (G/T = 0). where CODE10 is the decimal equivalent of the digital output code as shown in Table 2. The digital outputs D0-D11 are high impedance when the MAX1206 is in power-down (PD = high). D0-D11 go high impedance within 10ns of the rising edge of PD and become active within 10ns of PD's falling edge. Keep the capacitive load on the MAX1206 digital outputs D0-D11 as low as possible (<15pF) to avoid large digital currents feeding back into the analog portion of the MAX1206 and degrading its dynamic performance. The addition of external digital buffers on the digital outputs isolate the MAX1206 from heavy capacitive loads. To improve the dynamic performance of the MAX1206, add 220 resistors in series with the digital outputs close to the MAX1206. Refer to the MAX1211 evaluation kit schematic for an example of the digital outputs driving a digital buffer through 220 series resistors.
2 x VREF 4096 VREF
VREF = VREFP - VREFN VREF
0x800 0x801 0x803
GRAY OUTPUT CODE (LSB)
0xC01 0xC00 0x400
0x002 0x003 0x001 0x000
-2047 -2045 -1 0 +1 +2045 +2047
DIFFERENTIAL INPUT VOLTAGE (LSB)
Figure 7. Gray Code Transfer Function (G/T = 1)
Power-Down Input (PD)
The MAX1206 has two power modes that are controlled with the power-down digital input (PD). With PD low, the
MAX1206 is in its normal operating mode. With PD high, the MAX1206 is in power-down mode.
______________________________________________________________________________________
21
40Msps, 12-Bit ADC MAX1206
BINARY-TO-GRAY CODE CONVERSION 1) THE MOST SIGNIFICANT GRAY-CODE BIT IS THE SAME AS THE MOST SIGNIFICANT BINARY BIT. D11 0 0 1 1 1 D7 0 1 0 0 D3 1 1 0 D0 0 BIT POSITION BINARY GRAY CODE
GRAY-TO-BINARY CODE CONVERSION 1) THE MOST SIGNIFICANT BINARY BIT IS THE SAME AS THE MOST SIGNIFICANT GRAY-CODE BIT. D11 0 0 1 0 0 D7 1 1 1 0 D3 1 0 1 D0 0 BIT POSITION GRAY CODE BINARY
2) SUBSEQUENT GRAY-CODE BITS ARE FOUND ACCORDING TO THE FOLLOWING EQUATION: GRAYX = BINARYX + BINARYX + 1 WHERE + IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH TABLE BELOW) AND X IS THE BIT POSITION. GRAY10 = BINARY10 + BINARY11 GRAY10 = 1 + 0 GRAY10 = 1
2) SUBSEQUENT BINARY BITS ARE FOUND ACCORDING TO THE FOLLOWING EQUATION: BINARYX = BINARYX+1 + GRAYX WHERE + IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH TABLE BELOW) AND X IS THE BIT POSITION. BINARY10 = BINARY11 + GRAY10 BINARY10 = 0 + 1 BINARY10 = 1
D11 0 0 + 1 1 1 1
D7 0 1 0 0
D3 1 1 0
D0 0
BIT POSITION BINARY GRAY CODE 0
D11 1 + 0 1 0 0
D7 1 1 1 0
D3 1 0 1
D0 0
BIT POSITION GRAY CODE BINARY
3) REPEAT STEP 2 UNTIL COMPLETE GRAY9 = BINARY9 + BINARY10 GRAY9 = 1 + 1 GRAY9 = 0
3) REPEAT STEP 2 UNTIL COMPLETE BINARY9 = BINARY10 + GRAY9 BINARY9 = 1 + 0 BINARY9 = 1
D11 0 0 1 1 + 1 0 1
D7 0 1 0 0
D3 1 1 0
D0 0
BIT POSITION BINARY GRAY CODE 0 0
D11 1 + 1 1 0 0
D7 1 1 1 0
D3 1 0 1
D0 0
BIT POSITION GRAY CODE BINARY
4) THE FINAL GRAY CODE CONVERSTION IS: D11 0 0 1 1 1 0 1 0 D7 0 1 1 1 0 1 0 0 D3 1 1 1 0 0 1 D0 0 0 BIT POSITION BINARY GRAY CODE
4) THE FINAL BINARY CONVERSTION IS: D11 0 0 1 1 0 1 0 1 D7 1 0 1 1 1 0 0 0 D3 1 1 0 1 1 0 D0 0 0 BIT POSITION GRAY CODE BINARY
EXCULSIVE OR TRUTH TABLE A 0 0 1 1 B 0 1 0 1 Y = A + 0 1 1 0 B
Figure 8. Binary-to-Gray and Gray-to-Binary Code Conversion 22 ______________________________________________________________________________________
40Msps, 12-Bit ADC
The power-down mode allows the MAX1206 to efficiently use power by transitioning to a low-power state when conversions are not required. Additionally, the MAX1206 parallel output bus goes high impedance in power-down mode, allowing other devices on the bus to be accessed. In power-down mode, all internal circuits are off, the analog supply current reduces to 0.045mA, and the digital supply current reduces to 6A. The following list shows the state of the analog inputs and digital outputs in power-down mode: * INP, INN analog inputs are disconnected from the internal input amplifier (Figure 3). * REFOUT has approximately 17k to GND. * REFP, COM, REFN go high impedance with respect to VDD and GND, but there is an internal 4k resistor between REFP and COM, as well as an internal 4k resistor between REFN and COM. * D0-D11, DOR, and DAV go high impedance. * CLKP, CLKN clock inputs go high impedance (Figure 4). The wake-up time from power-down mode is dominated by the time required to charge the capacitors at REFP, REFN, and COM. In internal reference mode and buffered external reference mode, the wake-up time is typically 10ms. When operating in the unbuffered external reference mode, the wake-up time is dependent on the external reference drivers.
MAX1206
24.9 INP 12pF 0.1F VIN N.C. 1 2 3 T1 6 5 4 2.2F 0.1F MAX1206
COM
MINICIRCUITS TT1-6 OR T1-1T
24.9 INN 12pF
Figure 9. Transformer-Coupled Input Drive for Input Frequencies Up to Nyquist
Applications Information
Using Transformer Coupling
In general, the MAX1206 provides better SFDR and THD with fully differential input signals than singleended input drive. In differential input mode, evenorder harmonics are lower as both inputs are balanced, and each of the ADC inputs only requires half the signal swing compared to single-ended input mode. An RF transformer (Figure 9) provides an excellent solution to convert a single-ended input source signal to a fully differential signal, required by the MAX1206 for optimum performance. Connecting the center tap of the transformer to COM provides a VDD / 2 DC level shift to the input. Although a 1:1 transformer is shown, a step-up transformer can be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion. The configuration of Figure 9 is good for input frequencies up to Nyquist (fCLK / 2). The circuit of Figure 10 converts a single-ended input signal to fully differential just as in Figure 9. However,
Figure 10 utilizes an additional transformer to improve the common-mode rejection, allowing high-frequency signals beyond the Nyquist frequency. The two sets of 49.9 termination resistors provide an equivalent 50 termination to the signal source. The second set of termination resistors connects to COM, providing the correct input common-mode voltage. Two 0 resistors in series with the analog inputs allow high IF input frequencies. These 0 resistors can be replaced with lowvalue resistors to limit the input bandwidth.
Single-Ended AC-Coupled Input Signal
Figure 11 shows an AC-coupled, single-ended input application. The MAX4108 provides high speed, high bandwidth, low noise, and low distortion to maintain the input signal integrity.
Buffered External Reference Drives Multiple ADCs
The buffered external reference mode allows for more control over the MAX1206 reference voltage and allows multiple converters to use a common reference. The REFIN input impedance is >50M. Figure 12 shows the MAX6062 precision bandgap reference used as a common reference for multiple converters. The 2.048V output of the MAX6062 passes through a one-pole 10Hz lowpass filter to the MAX4250. The MAX4250 buffers the 2.048V reference before its
23
______________________________________________________________________________________
40Msps, 12-Bit ADC MAX1206
0* 0.1F VIN N.C. 1 2 3 T1 6 5 4 49.9 0.5% 49.9 0.5% N.C. 1 2 3 T1 6 5 4 49.9 0.5% N.C. 0.1F INP 12pF MAX1206 COM 4.7F 49.9 0.5%
MINICIRCUITS ADT1-1WT
MINICIRCUITS ADT1-1WT
0* INN 12pF
*0 RESISTORS CAN BE REPLACED WITH LOW-VALUE RESISTORS TO LIMIT THE INPUT BANDWIDTH.
Figure 10. Transformer-Coupled Input Drive for Input Frequencies Beyond Nyquist
output is applied to the REFIN input of the MAX1206. The MAX4250 provides a low offset voltage (for high gain accuracy) and a low noise level.
Unbuffered External Reference Drives Multiple ADCs
The unbuffered external reference mode allows for precise control over the MAX1206 reference and allows multiple converters to use a common reference. Connecting REFIN to GND disables the internal reference, allowing REFP, REFN, and COM to be driven directly by a set of external reference sources. Figure 13 shows the MAX6066 precision bandgap reference used as a common reference for multiple converters. The 2.500V output of the MAX6066 is followed by a 10Hz lowpass filter and precision voltage-divider. The MAX4254 buffers the taps of this divider to provide the +2.000V, +1.500V, and +1.000V sources to drive REFP, REFN, and COM. The MAX4254 provides a low offset voltage and low noise level. The individual voltage followers are connected to 10Hz lowpass filters, which filter both the reference voltage and amplifier noise to a level of 3nV/Hz. The 2.000V and 1.000V reference voltages set the differential full-scale range of the associated ADCs at 1.000V. The common power supply for all active components removes any concern regarding power-supply sequencing when powering up or down. With the outputs of the MAX4254 matching better than 0.1%, the buffers and subsequent lowpass support as many as 8 ADCs.
VIN MAX4108 100
0.1F 12pF 24.9
MAX1206
INP
2.2F 100 24.9
0.1F COM
INN 12pF
Figure 11. Single-Ended, AC-Coupled Input Drive
Grounding, Bypassing, and Board Layout
The MAX1206 requires high-speed board layout design techniques. Refer to the MAX1211 evaluation kit data sheet for a board layout reference. Locate all bypass capacitors as close to the device as possible, prefer24
ably on the same side as the ADC, using surfacemount devices for minimum inductance. Bypass VDD to GND with a 0.1F ceramic capacitor in parallel with a 2.2F ceramic capacitor. Bypass OVDD to GND with a 0.1F ceramic capacitor in parallel with a 2.2F ceramic capacitor. Multilayer boards with ample ground and power planes produce the highest level of signal integrity. All MAX1206 GNDs and the exposed backside paddle must be connected to the same ground plane. The MAX1206 relies on the exposed backside paddle connection for a low-inductance ground connection. Use mulitple vias to connect the top-side ground to the bottom-side ground. Isolate the ground plane from any noisy digital system ground planes such as a DSP or output buffer ground.
______________________________________________________________________________________
40Msps, 12-Bit ADC MAX1206
+3.3V
0.1F VDD 39 1 0.1F 2 16.2k MAX6062 1F 4 3 2 10F 6V 47F 6V 38 0.1F REFOUT GND COM 3 MAX4250 3 5 1 47 2.048V 0.1F 0.1F MAX1206 REFN 2 REFIN REFP 1 *1F
2.2F
0.1F
10F
0.1F
0.1F
2.2F
1.47k NOTE: ONE FRONT-END REFERENCE CIRCUIT PROVIDES 15mA OF OUTPUT DRIVE. +3.3V
0.1F VDD 39 0.1F MAX1206 REFN 2 REFIN REFP 1 *1F
2.2F
0.1F
10F
0.1F 38 0.1F REFOUT GND COM 3 0.1F 2.2F
*PLACE AS CLOSE TO THE DEVICE AS POSSIBLE.
Figure 12. External Buffered (MAX4250) Reference Drive Using a MAX6062 Bandgap Reference
Route high-speed digital signal traces away from the sensitive analog traces. Keep all signal lines short and free of 90 turns. Ensure that the differential analog input network layout is symmetric and that all parasitics are balanced equally. Refer to the MAX1211 evaluation kit data sheet for an example of symmetric input layout.
Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. This straight line is either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX1206 are guaranteed by design using the best-straight-line fit method.
______________________________________________________________________________________
25
MAX1206
40Msps, 12-Bit ADC
Figure 13. External Unbuffered Reference Driving 8 ADCs with MAX4254 and MAX6066
+3.3V 0.1F VDD 1 2.500V 2 MAX1206 2 3 3 1 1F 21.5k 1% 1.47k 1.500V 47 0.1F VDD 1 1.000V 47 330F 6V 1.47k 0.1F 3 2.2F 0.1F COM GND REFIN 39 10F 0.1F *1F 2 REFN REFP MAX1206 REFOUT 38 0.1F 2.2F 1/4 MAX4254 7 6 0.1F 4 14 1/4 10 8 21.5k 1% 9 10F 6V 21.5k 1% 11 MAX4254 1/4 MAX4254 1.47k 21.5k 1% 10F 6V 330F 6V 10F 6V 330F 6V 2.2F 0.1F 2 47 3 COM GND 1/4 MAX4254 2.000V 0.1F REFIN 39 21.5k 1% REFN 10F 0.1F *1F REFP REFOUT 0.1F 0.1F MAX6066 1 38 2.2F 5 +3.3V UNCOMMITTED
26
NOTE: ONE FRONT-END REFERENCE CIRCUIT SUPPORTS UP TO 8 MAX1206s.
+3.3V
1M
12
______________________________________________________________________________________
1M
13
*PLACE AS CLOSE TO THE DEVICE AS POSSIBLE.
40Msps, 12-Bit ADC
Signal-to-Noise Ratio (SNR)
CLKN CLKP tAD ANALOG INPUT tAJ SAMPLED DATA
MAX1206
For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC's resolution (N bits): SNRdB[max] = 6.02dB x N + 1.76dB In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first six harmonics (HD2-HD7), and the DC offset.
T/H
HOLD
TRACK
HOLD
Figure 14. T/H Aperture Timing
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency, excluding the fundamental and the DC offset.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. ENOB for a full-scale sinusoidal input waveform is computed from: SINAD - 1.76 ENOB = 6.02
Offset Error
Ideally, the midscale MAX1206 transition occurs at 0.5 LSB above midscale. The offset error is the amount of deviation between the measured transition point and the ideal transition point.
Gain Error
Ideally, the positive full-scale MAX1206 transition occurs at 1.5 LSB below positive full scale, and the negative full-scale transition occurs at 0.5 LSB above negative full scale. The gain error is the difference of the measured transition points minus the difference of the ideal transition points.
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first six harmonics of the input signal to the fundamental itself. This is expressed as: V22 + V32 + V4 2 + V52 + V62 + V72 THD = 20 x log V1
Aperture Jitter
Figure 14 depicts the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (Figure 14).
where V1 is the fundamental amplitude, and V2 through V7 are the amplitudes of the 2nd- through 7th-order harmonics (HD2-HD7).
Overdrive Recovery Time
Overdrive recovery time is the time required for the ADC to recover from an input transient that exceeds the full-scale limits. The MAX1206 specifies overdrive recovery time using an input transient that exceeds the full-scale limits by 10%.
Single-Tone Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS amplitude of the next-largest spurious component, excluding DC offset.
27
______________________________________________________________________________________
40Msps, 12-Bit ADC MAX1206
Two-Tone Spurious-Free Dynamic Range (SFDRTT)
SFDRTT represents the ratio, expressed in decibels, of the RMS amplitude of either input tone to the RMS amplitude of the next-largest spurious component in the spectrum, excluding DC offset. This spurious component can occur anywhere in the spectrum up to Nyquist and is usually an intermodulation product or a harmonic.
39 REFIN
Pin Configuration
34 OVDD 35 GND 33 DAV
TOP VIEW
40 G/T
38 REFOUT
36 VDD
32 I.C.
31 I.C. 30 D0 29 D1 28 D2 27 D3 26 D4 25 D5 24 D6 23 D7 22 D8 21 D9
Intermodulation Distortion (IMD)
IMD is the ratio of the RMS sum of the intermodulation products to the RMS sum of the two fundamental input tones. This is expressed as:
2 2 V 2+V IMP1 IMP2 + * * * * + VIMPn IMD = 20 x log V12 + V22
REFP REFN COM GND INP INN GND DCE CLKN
1 2 3 4 5 6 7 8 9
EXPOSED PADDLE (GND)
CLKP 10 CLKTYP 11 VDD 12 VDD 13 VDD 14 VDD 15 GND 16 OVDD 17 DOR 18 D11 19 D10 20
The fundamental input tone amplitudes (V1 and V2) are at -7dBFS. Fourteen intermodulation products (VIMP_) are used in the MAX1206 calculation. The intermodulation products are the amplitudes of the output spectrum at the following frequencies: * 2nd-order intermodulation products: f1 + f2, f2 - f1 * 3rd-order intermodulation products: 2 x f1 - f2, 2 x f2 - f1, 2 x f1 + f2, 2 x f2 + f1 * 4th-order intermodulation products: 3 x f1 - f2, 3 x f2 - f1, 3 x f1 + f2, 3 x f2 + f1 * 5th-order intermodulation products: 3 x f1 - 2 x f2, 3 x f2 - 2 x f1, 3 x f1 + 2 x f2, 3 x f2 + 2 x f1
THIN QFN 6mm x 6mm x 0.8mm
intermodulation products are 2 x f1 - f2, 2 x f2 - f1, 2 x f1 + f2, 2 x f2 + f1.
37 PD
MAX1206
Chip Information
TRANSISTOR COUNT: 18,700 PROCESS: CMOS
3rd-Order Intermodulation (IM3)
IM3 is the total power of the 3rd-order intermodulation products to the Nyquist frequency relative to the total input power of the two input tones f1 and f2. The individual input tone levels are at -7dBFS. The 3rd-order
28
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40Msps, 12-Bit ADC
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.) Note: For the MAX1206 exposed pad variations, the package code is T4066-3.
QFN THIN 6x6x0.8.EPS
MAX1206
D2 D D/2 k
C L
b D2/2
E/2 E2/2 E (NE-1) X e
C L
E2
k
e (ND-1) X e
L
e L
C L C L
L1 L L
e
e
A1
A2
A
PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm
21-0141
E
1 2
NOTES: 1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994. 2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES. 3. N IS THE TOTAL NUMBER OF TERMINALS. 4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1 IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE. 5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP. 6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY. 7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION. 8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT FOR 0.4mm LEAD PITCH PACKAGE T4866-1. 10. WARPAGE SHALL NOT EXCEED 0.10 mm.
PACKAGE OUTLINE 36, 40, 48L THIN QFN, 6x6x0.8mm
21-0141
E
2 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 29 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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